1. Field of the Invention
The present invention generally relates to a method for post silicide spacer removal, and more particularly to a method for removing a nitride spacer while protecting the suicide layer from damage.
2. Description of the Related Art
It is known that appropriately applied stress in a device channel can be beneficial to the performance of the device. The applied stress may be obtained through, among other means, the use of a stressed nitride liner as a contact etch stop layer. It is also known that the stress from the nitride liner is more efficiently transferred to a device channel when it is brought in close proximity to the device channel. One means of accomplishing this is to remove the sidewall spacers typically employed in the art prior to stressed nitride liner deposition. The sidewall spacers are commonly employed for a number of purposes, such as offsetting the heavily doped source and drain regions of the metal-oxide-silicon field effect transistor (MOSFET) from the channel region and to block silicidation between the source and drain regions of the MOSFET and the gate electrode.
Additionally, the thickness of the stressed liner that can be employed is often limited by the aspect ratio of the spaces to be filled with the stressed liner. This limitation can be mitigated somewhat by removing the sidewall spacers from the gate electrode, reducing the aspect ratios of the most densely placed gate electrodes, reducing the aspect ratios of the most densely placed gate structures, thus enabling the use of thicker stressed liners.
Thinning or removing the spacer is quite difficult, however, due to the proclivity of a majority of conventional etches to attack silicide along with the oxide and/or nitride spacer.
Conventionally, there exist several known methods for removing sidewall spacers. One such method involves removal of the spacer prior to silicidation of the device. A problem with this process is that, upon silicidation of the device, it is difficult to control the lateral position of the silicide in relation to the gate. Thus, this first method of spacer removal requires one to use a thin liner material, such as oxide, positioned immediately beneath the spacer to be removed to block silicidation between the source and drain regions of the device and the gate electrode.
Typical surface preparation methods for optimal silicide formation include oxide and nitride etches, which attack the thin liner material, particularly at the edges, where two-dimensional etching effects are present. As a result, the controllability of such a process is poor, and product yield loss is a likely result.
A second method of spacer removal involves removal of the spacer after silicide formation is complete. A “brute-force” approach is impractical, however, requiring the use of an etch chemistry which can effectively remove the nitride spacer but is selective to oxide, heavily doped silicon, and silicide. This puts many constraints on the type of etching that may be used to remove the spacer. In addition, because the silicide is exposed to the etch, the suicide resistance may be degraded, resulting in an undesirable increase in extrinsic resistance on the MOSFET.
Presently there are no conventional post silicide spacer removal methods that allow the nitride spacer to be removed while protecting the silicide from attack.